1. Field of the Invention
The present invention relates to a memory system, in particular, to a memory system including a synchronous dynamic random access memory (simply referred to as an `SDRAM`, hereinafter).
The present invention also relates to a memory control system for control of the memory system.
The present invention also relates to an image processing system such as a scanner apparatus, a printer, a duplicator (such as an electrophotographic duplicator), a facsimile apparatus and so forth. The memory system is as an image memory for storing image data therein.
2. Description of the Related Art
In the related art, a dynamic random access memory (simply referred to as a `DRAM`, hereinafter) has been used as the memory system in the image processing system which controls storage and reading of image information. In this technical field, as high-speed information processing of a micro CPU and a printer has been achieved, it is required to enlarge the capacity for storing image information and, also provide for high-speed storage of image information. A static random access memory (simply referred to as a `SRAM`, hereinafter) has been used recently in order to achieve high-speed storage of image information. However, in order to improve resulting image quality, storage capacity is required to be further enlarged and, thus, power consumption for the storage is increased which leads to increased costs.
When the large-capacity DRAM and high-speed operating SRAM are used for storing image information, the maximum power consumption for refreshing the DRAM is large and, thus, an extra power supplying system may be required and costs for a power supplying unit increase. Thus, the size of the entire system may be enlarged.
In the related art, a DRAM in a high-speed page mode or in a static column mode is used as an image memory in order to achieve a low-cost, large-capacity image memory.
It is possible to perform random access in high speed on the high-speed-page-mode DRAM to the same address by re-inputting column address strobe (the term "column address strobe" will be abbreviated as "CAS", hereinafter) and a column address in which asserting of row address strobe (the term "row address strobe" will be abbreviated as "RAS" hereinafter) is kept.
Similarly, it is possible to perform high speed access on the static-column-mode DRAM to a same-line address by changing a column address in which asserting of the RAS is kept. Further, because it is not necessary to strobe a column address using CAS, high speed access can be achieved.
In a nibble-mode DRAM, sequential access to data at an address as a result of incrementing the two least significant bits is performed when CAS is toggled in a state in which asserting of RAS is kept after finishing an ordinary access. Although burst access can be performed for only four words in the nibble-mode DRAM, high-speed access can be performed in comparison to the other-mode DRAMs.
However, a possible high-speed access in this case corresponds to be a cycle time on the order of 40 nanoseconds (25 MHz) at the most. If further improvement of the access speed is to be performed, it is necessary to increase bus width or to use an expensive SRAM. If bus width is increased, improvement of access speed is possible. However, various problems arise such as the relevant control circuit becoming complicated, delay time becoming longer, and a non-dividable unit of the relevant memory system being enlarged.
Recently, an SDRAM has been proposed in Japanese Laid-Open Patent Application No.5-120114. The SDRAM was obtained by making the above-described DRAM be a completely synchronous type. In use of the SDRAM, entry and refreshing of a load address and a column address is performed by inputting a relevant command at the rising edge of a clock pulse.
In detail, with regard to data reading, although the time required for accessing a first data is the same as that in the DRAM case, subsequent data is output for each clock pulse. The order in which data is sequentially accessed in this time is predetermined as a result of mode setting and, thus, it is not necessary to input a relevant column address for each clock pulse.
With regard to data writing, data can be input for each clock pulse from first data. Further, frequency of the clock pulses is high, specifically 100 MHz. Therefore, high-speed access can be achieved.
Further, because the SDRAM is of the completely synchronous type, a relatively simple circuit can do well as a relevant control circuit. In fact, an input signal can be easily produced by producing a signal which only has a timing for providing a condition of set-up time and hold time for a relevant one of the clock pulses. (With regard to details of the set-up time and the hold-time, see NEC, IC Memory Dynamic RAM, 1994, Data Book, page 808.) The timing of an output signal can be easily known from the timing of the clock pulses.
Thus, by using the SDRAM, it is possible to provide a memory system by which the information processing rate of a relevant CPU can be improved.
As mentioned above, entry and refreshing of a load address and a column address is performed by inputting a relevant command at a rising edge of a clock pulse in use of the SDRAM. Further, when a power-down mode activating/deactivating command and self-refreshing command is input using a clock enable signal (CKE), a register for inputting the power-down mode activating/deactivating command and self-refreshing command is provided in an ASIC which controls the memory. The power-down mode is a mode which may be activated in an active stand state (after a bank active command is written) or in a precharge standby state (after a precharge command is written) in the SDRAM. The power-down mode can be activated by causing the CKE signal to be at a low level, and by activating the power-down mode, energy consumed in the SDRAM can be saved. A CPU may write a relevant command in the register and thus entry and activating the power-down mode and execution of self-refreshing may be performed. Thus, the memory control system is complicated. (With regard to a detail of the power-down mode and CKE signal, see NEC, IC Memory Dynamic RAM, 1994, Data Book, Document No.ID-3394, published March 1994, printed in Japan by NEC Corporation, `16M bit Synchronous DRAM`, pages 777, 786, and 787, and 16M SDRAM User's Manual (provisional edition) (written with the Japanese language), Doc.No.SUD-W-0103-3, published Jun. 3, 1995, by Semiconductor Application Technology Division, Memory Technology Department, NEC corporation, Page 3-28, `Power-Down Operation` (command No14).)
Further, time is required for activating and deactivating the power down mode. Therefore, if an SDRAM is used for storing data, such as instruction data, which is written in and read out relatively frequently, applying the power-down mode to such an SDRAM may degrade the writing/reading speed. If a memory monitoring circuit is provided so as to determine whether or not a particular SDRAM is used for storing data which is written in and read out relatively frequently, it is possible to activate the power-down mode appropriately depending on frequency of use of the memory. However, the provision of such a memory monitoring circuit makes the memory control system complicated.
Further, once activating/deactivating of the power-down mode are specified for an area of the memory, the activating/deactivating of the power-down mode are performed regardless of contents of data stored in the area of the memory.
Further, when the power-down mode is used for the SDRAM , it is necessary to cause the clock enable signal (CKE) to change at high speed so as to activate and deactivate the power-down mode in a precisely appropriate timing. The clock enable signal (CKE) can be used to invalidate a rising edge of the clock pulses as well as for controlling activating/deactivating of the power-down mode. However, invalidating a rising edge of the clock pulse is not needed in all systems. Hardware provided for control of the clock enable signal (CKE) can be simplified in a case where invalidating a rising edge of the clock pulse is not needed. However, even in this case, it is necessary to control the clock enable signal (CKE) at high speed in order to effectively use the power-down mode.
In particular, when many SDRAMs are used as an image memory for storing image data, the clock enable signal (CKE) is to be supplied for a large amount of load. For this purpose, buffering is performed. Further, different from the cases of the RAS, CAS signals, the clock enable signal is to provide condition for a set-up time and a hold time for a rising edge of a relevant one of the clock pulses.
When a relevant control circuit for the SDRAMs is provided by an ASIC, many external pins are used for communicating the clock enable signals (CKE) or, an external high-speed buffer or D-flip-flop is to be provided. Further, many signal wires are present and high wave quality of the signals communicated through the signal wires is essential.
If the SDRAM is used as an image memory, because it is not necessary that image data is always present in an image forming operation, it is unnecessary to always store contents present in the memory.